Semiconductor device with redundancy circuit and means for activating same

ABSTRACT

A semiconductor device such as a DRAM with many signal line circuits is also provided with a redundancy circuit and is so structured that when one of the signal line circuits is defective and the fuse contained by such a defective signal line circuit is cut off to inactivate it, an input signal which would select the inactivated signal line circuit will automatically select the redundancy circuit.

BACKGROUND OF THE INVENTION

This invention relates to a semiconductor device with spare signal linecircuits or so-called redundancy circuits for salvaging bits containingdefective signal lines.

The yield of semiconductor devices such as memory devices like DRAMsusually becomes low if an attempt is made to increase their memorycapacity by miniaturizing them, to make their production process morecomplicated or to increase their chip size. In order to prevent such adrop in the yield, it has been known to provide memory chips not onlywith the ordinary bit lines, word lines and memory cells but also withspare bit lines, word lines and memory cells or the so-called redundancylines such that a defective component which is originally intended foruse can be replaced by a spare component. A certain fraction of chipswhich would otherwise be deemed defective can be saved by suchreplacement before they are packaged. The conventional method ofreplacing a defective line has been to activate a spare bit line or wordline, assigning thereto the same address as that of the defective lineand to inactivate the bit line or word line of the defective bit.

FIG. 2 is a circuit diagram of a conventional redundancy circuit by wayof which a static method of using redundancy lines is explained below.For the purpose of simplifying the explanation, 2-bit addresses areconsidered. In FIG. 2, bit lines originally intended for use are BIT11,BIT11-BIT14, BIT14 while BITR and BITR represent redundant bit lines.Let us now consider the situation where the pair of bit lines BIT11 andBIT11 is defective and to be replaced respectively by the redundancy bitlines BITR and BITR. First, the fuse FUSE11 is cut off in order toinactivate the bit lines BIT11 and BIT11. Since this cuts off thesignals from the NAND gate NAND11, the voltage level at the node 20becomes "H" because of the transistor TP6 with a small β value while thenode 21 becomes "L" through the inverter gate INV11. As a result, thebit lines BIT11 and BIT11 become disconnected forever electrically fromthe data lines D and D. Next, when the fuse FUSER5 is cut off in orderto activate redundant lines corresponding to the bit lines BIT11 andBIT11, the node 22 becomes "H" similarly because of the transistor TP5with a small β value and the nodes 23 and 24 respectively become "L" and"H" such that all transistors TP11-TP14 and TN1-TN4 become transmissiveand the address signals A₀, A₀, A₁ and A₁ are respectively transmittedto the nodes 25 and 26. In addition, the fuses FUSER2 and FUSER4 are cutoff in order to eliminate the unwanted address signals A₀ and A₁ suchthat the bit lines BIT11 and BIT11 become inactive and redundant bitlines BITR and BITR become active.

A disadvantage associated with the circuit shown in FIG. 2 is that manylarge elements such as the fuses FUSER1-FUSER5 are required in theredundancy circuit. This means that the area on a chip occupied by theredundancy circuit becomes large and since a large number of fuses mustbe cut off according to the method of operation described above, a longtime period is wasted in the replacement, resulting in an increase inthe cost of the product.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to provide asemiconductor device with a redundancy circuit with which the chip areaneed not be increased and the time required for replacement operationcan be reduced.

The above and other objects of the present invention are achieved byproviding a semiconductor device such as a DRAM having many signal linecircuits each containing a fuse and a redundancy circuit connected insuch a way that when the fuse of a defective one of the signal linecircuits is cut off to inactivate it, the redundancy circuitautomatically becomes selected by a signal which would select thedefective signal line circuit if its fuse has not been cut.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and form a part ofthe specification, illustrate an embodiment of the present inventionand, together with the description, serve to explain the principles ofthe invention. In the drawings:

FIG. 1 is a circuit diagram of a semiconductor memory device with aredundancy circuit embodying the present invention, and

FIG. 2 is a circuit diagram of a conventional type of semiconductordevice with redundancy circuits.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment of the present invention is described below but thepresent invention is not intended to be limited by this illustrativeexample.

In FIG. 1, numerals 1, 2, 3 and 4 indicate signal line circuits. Thefirst signal line circuit 1 includes a NAND gate NAND1 of which theinput terminals are connected to address buses A₁ and A₀, a circuitopening element (hereinafter referred to as a fuse) FUSE1 connected tothe output terminal of the NAND gate NAND1, an inverter gate INV1 with anode 5 defined between the inverter gate INV1 and the fuse FUSE1,transistors 7 and 8 which are connected to the node 6 on the output sideof the inverter gate INV1 for a switching control and are adapted toconnect bit line BIT1 with data D and bit line BIT1 with data line Dwhen switched on and another transistor TP1 for setting the node 5 at"H" voltage level. Each of the other signal line circuits 2, 3 and 4 isstructured identically. Corresponding components in these circuits areindicated by the same symbols.

The input terminals of the NAND gate NAND1 of the second signal linecircuit 2 are connected to the address buses A₁ and A₀, those of theNAND gate NAND1 of the third signal line circuit 3 are connected to theaddress buses A₁ and A₀, and those of the NAND gate NAND1 of the fourthsignal line circuit 4 are connected to the address buses A₁ and A₀.Similarly, the transistors 7 and 8 of the second signal line circuit 2are adapted to connect the data line D with bit line BIT2 and the dataline D with bit line BIT2, those of the third signal line circuit 3 areadapted to connect the data line D with bit line BIT3 and the data lineD with bit line BIT3, and those of the fourth signal line circuit 4 areadapted to connect the data line D with bit line BIT4 and the data lineD with bit line BIT4.

Numeral 9 indicates a spare signal line circuit. The spare signal linecircuit 9 includes transistors 10 and 11 adapted to connect the dataline D with a spare bit line BIT1R and the data line D with anotherspare bit line BIT1R when switched on, and an inverter gate INV1R forcontrolling the switching of the transistors 10 and 11. Additionaltransistors TP2 are individually provided to the signal line circuits 1,2, 3 and 4, each serving, when switched on, to connect the node 6 of thecorresponding signal line circuit 1, 2, 3, or 4 with its node 12.Numerals 13 each indicate a selection circuit which serves to transmitthe output of a NAND gate NAND1 to the corresponding transistor TP2.

In what follows, operation of the circuits shown in FIG. 1 and themethod of replacement are explained in detail. Let us assume thataddresses are given in two bits as done in connection with thedescription of the conventional circuit of FIG. 2, and consider first asituation where there is no defect in the four signal line circuits 1,2, 3 and 4 and the bit line BIT1 is the one to be selected. In thissituation, address buses A₁ and A₀ are both at "H" levels and only theoutput from the NAND gate NAND1 of the first signal line circuit 1becomes "L".

With consideration given only to the first signal line circuit 1, theaforementioned "L" signal from the NAND gate NAND1 causes the invertergate INV1 to output an "H" signal. The transistors 7 and 8 are therebyswitched on and the bit lines BIT1 and BIT1 are selected as explainedabove. Since the transistor TP2 is also in the ON condition in thissituation, however, the node 12 in the redundancy circuit 9 becomes "H"and the node 14 is "L" such that the spare bit lines BIT1R and BIT1R arenot selected. The bit lines BIT2-BIT4 and BIT2-BIT4 corresponding to theother signal line circuits 2, 3 and 4 are likewise not selected becausethe outputs from the NAND gates NAND1 in these signal line circuits 2, 3and 4 are all "H", causing the outputs from the corresponding invertergates INV1 to be "L". The transistors TP2 corresponding to these signalline circuits 2, 3 and 4 are also in the OFF condition.

Next, let us consider the situation where the bit line BIT1 and/or bitline BIT1 is defective. In this situation, the fuse FUSE1 is cut off,for example, by a laser light in order to replace the bit lines BIT1 andBIT1 by spare bit lines BIT1R and BIT1R. Thereafter, the node 5 becomes"H" because of the transistor TP1 and the node 6 becomes "L". This meansthat the bit lines BIT1 and BIT1 are inactivated forever and notselected. On the other hand, since the output from the NAND gate NAND1is "L" and the transistor TP2 is in the ON condition, the nodes 12 and14 respectively become "L" and "H" such that the spare bit lines BIT1Rand BIT1R are selected.

Thereafter, if the address buses A₀ and A₁ become "L" and "H",respectively, to select the bit lines BIT2 and BIT2, the output of theNAND gate NAND1 of the second signal line circuit 2 becomes "L", therebyswitching on the transistor TP2 corresponding to the second signal linecircuit 2. Since the node 6 in the second signal line circuit 2 is "H"at this moment, however, "H" signal is received at the node 12 of theredundancy circuit 9. This places the node 14 in the "L" level and thespare bit lines BIT1R and BIT1R are not selected.

The foregoing description of a preferred embodiment of the invention hasbeen presented for purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and many modifications and variations are possible in lightof the above teaching. For example, the present invention is not limitedto situations with 2-bit address signals. The circuit of FIG. 1 can beeasily modified for applications to 8-bit, 16-bit or even 32-bitmicrocomputers. Any conductive substance which can be cut off by theheat of laser light may be used as the circuit opening elements. Thepresent invention is characterized as requiring no elements such as adecoder circuit or a fuse for the selection of the redundancy lines andenabling a replacement operation to be completed easily merely byinactivating the defective section. As a result, the chip area need notbe increased to accommodate a selection circuit. The time required forreplacement can be shortened and the cost of chips can be reduced.

What is claimed is:
 1. A semiconductor device comprisinga plurality ofsignal line circuits each including a selecting line for transmitting aline selecting signal therethrough and a normally closed circuit openingelement, and a redundancy signal line circuit connected to each of saidsignal line circuits through a single transistor, said circuit openingelement connecting the gate of said transistor in series with saidselecting line of said signal line circuit, said device being sostructured that a defective one of said signal line circuits can beinactivated by opening said circuit opening element in said defectivesignal line circuit and that a signal applied to said inactivated signalline circuit serves to activate said redundancy signal line circuit. 2.The semiconductor device of claim 1 wherein said circuit opening elementis a fuse which can be opened by a laser.